1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a multi-level nonvolatile semiconductor memory device including multi-level memory cells and corresponding page buffers.
A claim of priority is made to Korean Patent Application No. 10-2006-15795, filed on Feb. 17, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
Non-volatile semiconductor memory devices have many distinguishing characteristics. One such characteristic includes the ability to preserve stored data even in the event of power loss to the semiconductor memory device. Furthermore, semiconductor memory devices include a number of memory cells. To this end, various types of memory cells appropriate for non-volatile semiconductor memory devices are known. One such memory cell is a transistor type memory cell.
FIG. 1 illustrates a transistor type memory cell MC. In general, the transistor type memory cell MC includes a number of components. For example, these components include a current path formed between a source S and a drain D on a semiconductor substrate. The components also include a floating gate FG formed between a dielectric oxide DOX and a gate oxide GOX. Furthermore, the components include a control gate CG.
Each component of the cell MC may perform one or more functions. For example, the floating gate FG traps electrons. These trapped electrons establish a threshold voltage of the memory cell MC. This established threshold voltage may be used in performing various operations on the cell MC. For example, when a non-volatile semiconductor memory device performs a read operation, the threshold voltage of the memory cell MC is detected and, thus, stored data is checked.
Typically, a transistor memory cell MC stores one of two data values. The two data values, as illustrated in FIG. 2, are determined by a threshold voltage that is set to one of two levels. For example, data is read as “1” when the threshold voltage of the memory cell MC is lower than a reference voltage VM, and data is read as “0” when the threshold voltage of the memory cell MC is higher than the reference voltage VM.
Due to the increase in demand for high integration density on semiconductor memory devices, efforts are being made towards increasing the amount of data that may be stored in a memory cell. To this end, semiconductor memory manufacturers have developed a 4-level memory cell.
FIG. 4 illustrates a 4-level memory cell. The illustrated 4-level memory cell can be programmed with one of four threshold voltage levels. As a result, the 4-level memory cell can store any one of four types of data, each data corresponding to a threshold voltage level. Therefore, a non-volatile semiconductor memory device having 4-level memory cells (hereinafter referred to as a “4-level non-volatile semiconductor memory device”) has a data storage capacity that is twice that of a non-volatile semiconductor memory device having 2-level memory cells (hereinafter referred to as a “2-level non-volatile semiconductor memory device”).
While the 4-level non-volatile semiconductor device has twice the data storage capacity of a 2-level non-volatile semiconductor device, it has several shortcomings. For example, in a 4-level memory cell, the margin of a threshold voltage between neighboring levels is very narrow (typically about 0.67 V.) Such a narrow margin between threshold voltages may lead to problems. For example, the stored voltage in each memory cell that represents a stored data value may change due to the leakage of electrons or the like. Accordingly, the stored voltage may cross over the threshold voltage range of that data value to a neighboring level threshold voltage that corresponds to a different data value. This crossing over of the threshold voltage in a memory cell to a neighboring level may cause the value of the data stored in a memory cell to be read incorrectly. Therefore, the reliability of a 4-level non-volatile semiconductor device may be reduced.
The present disclosure is directed towards overcoming one or more of the problems associated with the 4-level non-volatile semiconductor device.